Semidynamics Performs RISC–V Surgery
Semidynamics offers fully customized RISC–V CPUs for clients requiring capabilities beyond what’s readily available. The ability to maintain many outstanding memory requests boosts performance for applications with poor data locality.
In the 1970s, fast-food burger joint Burger King promised that customers could “have it their way.” Semidynamics (SMD) makes a similar promise, providing RISC–V core implementations adapted, without limit, to customer specifications. In- and out-of-order base cores (Avispado and Atrevido, respectively) support vector operations and the ability to manage up to 128 outstanding memory requests.
Available for customization today, both base cores are 64-bit superscalar CPUs—Avispado is two-way with five execution units and Atrevido is three-way with six units. Paired with the integer core is a beefy vector unit. Vector registers can be 4,096 bits wide, with a datapath of up to 2,048 bits. The out-of-order memory-request feature, which SMD brands Gazzillion, targets applications such as AI and high-performance computing (HPC) that gather noncontiguous data. The company can customize, augment, or remove any of these features.
Roger Espasa leads the self-funded Barcelona-based company, having founded it in 2016. His background includes AI architecture at Esperanto and out-of-order design at Broadcom; he designed the AVX512 ISA at Intel. The company has been a design house since its founding; it remains so but is formalizing its offering. It currently has 35 employees. The product names derive from Spanish, with “avispado” translating as quick or clever and “atrevido” translating as daring.
Implemented in 7 nm, the default out-of-order Atrevido can clock up to 2.4 GHz. Given the vector unit’s 2,048-bit width and INT8 support, this performance yields AI throughput of 1.2 trillion operations per second (TOPS). Terms for purchase include nonrecurring engineering (NRE) charges for customization work, license fees, and royalties; the company withheld fee details.
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