PCI Express Gen6 Adopts PAM4
February 7, 2022 - Author: Bob Wheeler
In its sixth generation, PCI Express underwent the biggest changes since its debut in 2003. The PCIe 5.0 release in 2019 marked the end of the road for NRZ signaling, as another frequency doubling would be impractical. To maintain the same Nyquist frequency, PCIe 6.0 instead adopts PAM4 signaling to achieve 64Gbps, or 256GB/s of bidirectional bandwidth for a x16 interface. Last month, the PCI-SIG released the PCIe 6.0 (Gen6) specification to members only.
PAM4 (four-level pulse amplitude modulation) encodes 2 bits per unit interval (or symbol), doubling NRZ’s data rate at a given frequency. Operating at the same frequency as Gen5, Gen6 enables the reuse of PCB materials and connectors. The new modulation requires FEC to compensate for PAM4’s higher bit-error rate (BER) relative to NRZ. Whereas most Ethernet applications tolerate the added latency of a strong FEC code, PCIe has strict latency requirements, the importance of which has increased because new protocols such as CXL share the PCIe physical layer.
To offset FEC overhead, PCIe 6.0 adopts a new flow-control unit (flit) as the minimum data transfer. Each 256-byte flit includes 236 bytes of transaction-layer (TLP) data followed a 6-byte data-link packet (DLP), an 8-byte CRC, and a 6-byte FEC code. Flits are more efficient for small payloads than traditional packets are, enabling PCIe 6.0 to more than double effective bandwidth over PCIe 5.0 for payloads up to 128 bytes across all read/write mixes.
Subscribers can view the full article in the Microprocessor Report.
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