P650 Pumps Up Performance by 50%
December 27, 2021 - Author: Jim Turley
Progress comes quickly in the microprocessor business, but even so, it’s rare to see a company upgrade its flagship’s performance by 50% in just six months. RISC-V vendor SiFive wants to establish its credentials as a viable Arm alternative, and not just on the basis of cost, but in performance and power efficiency. The CPU licensor is gaining ground on its British rival, but it still has a long way to go.
The new P650 core upgrades the P550 announced in July with an additional execution unit, larger caches, better branch prediction, a different load/store pipeline, hypervisor support, and a handful of other tweaks. Integer performance improves by 50%, according to the company’s simulations. Most of that gain is through more instructions per clock (IPC), with the remainder due to a 10% higher maximum clock frequency.
The P650 targets two relatively high-end markets: automotive automation and data-center accelerators. RTL should reach preview customers in 1Q22, with a general release around midyear. That timing puts initial production silicon around the end of 2023 and P650-based equipment sometime in 2024.
SiFive compares its P650 to Arm’s Cortex-A77, citing similar SPECint 2006 numbers. The RISC-V design should have a smaller die area, though, mostly because of its smaller caches. That feature was a primary charm of the P550, too: similar logic area but smaller caches yielding similar performance in less space, at least for some workloads. Semiconductors are in short supply, so a smaller die translates into more working devices per wafer, hence more product and more profit. Few CPU architects approach high-performance design that way, but it pays the bills.
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