Marvell Fills In Octeon 10

Author: Joseph Byrne

Marvell Fills In Octeon 10

Marvell has entered production of the smallest members of its Octeon 10 DPU family. Integrating eight Arm NeoverseN2 CPUs and sporting 100GbE ports, the Octeon CN102xx and CN103xx target communications systems requiring less data- and control-plane performance than the bigger Octeon 10 models.

Upgraded from a 16 nm process in the prior generation to 5 nm currently, the CN102 and CN103 differ primarily in their serdes rates. The former operates its serdes at up to 10 Gbps, enabling it to support PCIe Gen3 and 10GbE. The latter is faster, supporting 50 Gbps to enable PCIe Gen5 and, with four serdes lanes, 100GbE (subsequent references to the CN103 apply to the CN102 unless otherwise specified). As with past Octeon models, the new processors offload packet processing and encryption. The Octeon 10 family also adds AI acceleration.

Marvell refers to Octeon processors as data-processing units, but MPR uses that term for the main chip in a smart NIC. Although the CN103 could be the heart of a smart NIC, it’s more general than the typical DPU. It also targets control-plane processing in Ethernet switches, 5G small cells, SDWAN systems, and conventional firewalls and routers.

Marvell announced the Octeon 10 family in 2021 and is in full production on all models. Integrating up to 24 CPUs and more networking throughput, the CN106 entered production in Q3 2022. The company has also commenced production of a CN105 with up to 18 cores and accelerators for L1 and L2 applications in wireless networks.

The authoritative information platform to the semiconductor industry.

Discover why TechInsights stands as the semiconductor industry's most trusted source for actionable, in-depth intelligence.