HiSilicon Hi1105GFCV120 Wi-Fi 6/BT 5.2/SparkLink SoC Floorplan Analysis (IoTB)
This is a Basic Floorplan Analysis (BFR) of the HiSilicon Hi1105GFCV120_die found inside HiSilicon Hi1105GFCV120. The Hi1105GFCV120 was extracted from the Huawei Mate 60 Pro. The Hi1105GFCV120 die is fabricated using a two-layer passivation, ten layers of metal interconnect (one aluminum (Al) top metal layer and nine copper (Cu) layers), tungsten (W) contacts, shallow trench isolation (STI), a single polysilicon layer, and high-k metal gate (HKMG) finFET transistors. The observed minimum metal pitch contacted gate pitch and fin pitch are 68 nm, 96.0 nm and 48 nm, respectively. These critical dimensions, along with the observed features of the transistors, suggest that the Hi1105GFCV120 die was manufactured on 300 mm wafers using SMIC's 14 nm HKMG finFET process.
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