Flex Logix Drops Chips, Sticks With IP

Flex Logix is changing its business model, opting to offer its InferX block as IP and ceasing chip-building operations. It’ll serve chipmakers requiring either AI inference or DSP capability.

Bryon Moyer

Flex Logix is changing its business model from selling AI accelerator chips to licensing DSP- and AI-acceleration tiles for integration into SoCs that implement vision algorithms. Performance scales linearly with the number of tiles in many designs. Reconfigurability permits reusing a block for different functions at different times. Available for licensing now, the technology targets modern silicon processes.

Flex isn’t new to the intellectual property (IP) business: it’s been selling embedded FPGA (eFPGA) IP since before offering its chip, and it previously offered an AI/DSP block, calling it NNMax before renaming it InferX for its X1 chip. The company found that chip design wins were unlikely to generate large-enough volumes, prompting it to cease chip operations and refocus on IP.

The AI tools developed for the X1 chip support the licensed tiles. The company added estimators that inform designers of the number of tiles necessary to achieve their desired performance with their models. For customers developing DSP (not AI) functions, however, Flex remains in the loop, with designers submitting desired functions and the company implementing them in its eFPGA fabric.

The hardware is reconfigurable, both in the eFPGA block and in the multiply-accumulate (MAC) blocks. Inference exploits this explicitly to change layers; DSP applications are less likely to change, but can do so to swap workloads. In a 5 nm process, the company aims for 16 INT8 TOPS at 1 GHz and a typical power of 1 W for each tile. Loading a new layer or workload takes 3 μs at 800 MHz.