CFETs Stack Transistors Vertically
Author: Dick James
Complementary field-effect transistors (CFETs) promise to reduce silicon area by stacking NFETs above PFETs to create, for example, a vertical inverter that’s smaller than a traditional side-by-side inverter. The challenge is to do so with minimal complexity for overall net cost savings.
The recent IEEE International Electron Devices Meeting (IEDM) conference included a session on 3D-stacked transistors, which situate opposite-polarity FETs vertically one above the other, eliminating the N to P spacing from the cell footprint. The industry has dubbed these stacked transistors CFETs.
Whereas a planar inverter relies on constant lithography improvements to move transistors closer together, stacking them eliminates that concern. Instead, the now vertical distance between the transistors is set by epitaxial growth, which is more controllable and scalable. This approach increases the process and integration complexity substantially, but the potential 50% density increase is driving significant research efforts by leading-edge companies and research institutions.
Intel, Samsung, and TSMC each have projects investigating ways of implementing CFETs. Although they largely follow the same basic strategy, they differ in their details. Current work allows only the building of the transistors. Configuring them for useful logic will take further work, likely leveraging backside contacts. Commercial chips employing the final version of this technology are unlikely before the end of the decade.
Although this technology has the potential to save significant silicon area, the net cost impact depends on how implemented. Imec estimates that the extra layers add about 14% to cost while saving 50% in area, giving a net positive cost outcome. Intel estimates that if back contacts are used, cost comes out neutral.
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