Baidu Kunlun II A2S1CAXGA SoC Packaging Quick Look Analysis

Baidu Kunlun II A2S1CAXGA SoC Packaging Quick Look Analysis

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This is an Advanced Packaging Quick Look (APQ) summary document for the Baidu Kunlun Xin A2S1CAXGA processor, provided as a companion deliverable for the APQ-2312-801 project. The Baidu Kunlun Xin processor, also referred to as the Kunlun II, is the second-generation of the Baidu Kunlun processor series. While the first-generation Kunlun processor used Samsung’s Interposer-Cube (I-Cube) 2.5D packaging technology and included 16 GB of HBM memory connected to the processor die through an interposer, the second-generation Kunlun Xin comprises a single TSMC manufactured die flip-chip bonded to a printed wiring board (PWB) marking a significant change in packaging design. Both the first-generation Kunlun and the Kunlun Xin implement Baidu’s XPU architecture with the second-generation providing users with 128 TFLOPS (FP16) of compute speed, twice the performance the first-generation Kunlun, while consuming less power.

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