Arm Updates Automotive Offering

Author: Bryon Moyer

Arm Updates Automotive Offering

Arm’s latest automotive intellectual property (IP) offering includes not just four new CPUs but also an image-signal processor (ISP) and blocks that allow the assembling of a functionally safe compute cluster. Configuration options allow developers to target systems with a range of safety criticality.

The new CPUs include automotive versions of two CortexA models, the CortexA520AE and CortexA720AE; the CortexR82AE; and the Neoverse V3AE. The MaliC720AE is a new ISP that can take on workloads for computer vision and human viewing in parallel. These processors are accompanied by coherent and noncoherent interconnect, the Neoverse CMNS3AE and the CoreLink NI710AE, respectively. The CoreLink GIC720AE, a generic interrupt controller supporting mixed criticality, rounds out the offering.

Functional safety for automobiles is governed by ISO 26262 (MPR Aug 2022, “Functional Safety Moves to Chips”); systems must demonstrate resilience against deterministic errors—essentially design bugs—and random (or latent) faults—ones that arise unrelated to the quality of the original design. Systematic-fault elimination comes through the use of trusted tools; random faults are handled through additional circuitry. The standard specifies four automotive safety-integrity levels (ASIL); the most common ones are ASIL B for less-critical functions and ASIL D for the most critical.

All the new blocks meet ASIL D requirements for systematic faults. Depending on the block and configuration, random faults can achieve ASIL B or D. They’re all available for licensing.

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