Arm Adds Compute Subsystem for V3

Author: Bryon Moyer

Arm Adds Compute Subsystem for V3

Arm’s newest Neoverse compute-subsystem (CSS*) intellectual property (IP) offering provides scalable cache-coherent interconnect, shared cache, DRAM controllers, and other I/Os for the new Neoverse N3 and V3 CPU cores. The Neoverse CSS N3 succeeds the older CSS N2, whereas the Neoverse CSS V3 is the first CSS for the Neoverse V series.

The company’s popular Cortex CPUs are ubiquitous in embedded systems and smartphones across the board, but Neoverse CPUs target data-center applications, where x86 CPUs dominate. The x86 CPUs are sold as complete processor chips, not as IP. Arm’s CSS offering reduces the effort necessary to build a compute subsystem around a core, making it easier for a processor designer to build a data-center chip around the CPU.

The CSSs are built on platform technology that interconnects cores and provides access to DRAM and other I/Os. Those blocks have been improved from their prior versions, doubling potential maximum intercore bandwidth and increasing the maximum core count and last-level cache sizes. Each CSS, however, receives its own values for these resources, some of which Arm withheld.

The V3 and N3 cores are also new, but few details are available from the company. Select workload performance has improved by around 13% on the basis of data Arm provided.

The CSSs and CPUs are available for licensing now, but the company will disclose more CPU information following silicon evaluation, which should occur sometime this year. We expect the first processors using the new IP to achieve production in H2 2025.

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