AMD Ships 3D V-Cache Processors

AMD Ships 3D V-Cache Processors

The Ryzen 7 5800X3D PC processor and Milan X server processor use TSMC’s chip-on-wafer (CoW) technology to stack more cache on the compute die, improving game and HPC performance.
Linley Gwennap
Linley Gwennap

After disclosing its 3D V Cache technology last year, AMD is now shipping two high-end products that use the stacking technique. The Ryzen 7 5800X3D is the new top-of-the-line PC processor. For servers, the Milan X chips extend the third-generation Epyc lineup with a massive 768MB of L3 cache, speeding data-intensive applications. The Epyc products began shipping in March, with Ryzen following in April.

V Cache uses TSMC’s chip-on-wafer (CoW) technology to stack a 64MB SRAM die atop a Zen 3 compute chiplet (CCD). Since the eight-core CCD already has 32MB of L3 cache, the combination delivers 96MB of total cache. The 5800X3D has one CCD, but Milan X has eight, enabling 64 cores and a massive cache.

The new Ryzen has a 3.4GHz base speed and can boost to 4.5GHz. The previous 5900X can run slightly faster, up to 4.7GHz, in the same TDP; the extra V Cache power slows the 5800X3D. Thus, applications that don’t benefit from the extra cache, including most synthetic benchmarks, run slightly faster on the older part. But most games handle lots of data, yielding a 21% average gain over the 5900X for 1080p titles.

The flagship Epyc 7773X has a base speed of 2.2GHz—a bit lower than the 2.45GHz of the previous top-end model, the 7763. Fitting the extra power of the 512MB V Cache into the same 280W TDP causes this reduction. The boost clock, however, remains the same, while the list price jumps 11%. As with the PC version, the performance gain depends on the workload. AMD expects 10–40% gains for scientific (HPC) applications; one fluid-dynamics simulation nearly doubled in performance. Although the company positions Milan X for technical computing, the bigger cache should also benefit other server tasks that need to store as much data as possible in the cache.

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