• JEONGDONG CHOE, Ph. D., Senior Technical Fellow at TechInsights, Ottawa, Canada

    Key features of the cell structure, design and integration of the Micron 3D 32L FG-NAND device are discussed, and compared with Samsung’s 32L and 48L V-NAND device.

    The Intel/Micron 1st generation 3D TLC NAND with FG (floating gate) structure is finally on the market. TechInsights has torn down Micron’s Crucial MX300 750 GB 2.5-inch SSD and reverse engineered Micron’s 3D FG-NAND. The SSD has eight 3D NAND packages with 6FB22 NW852 package markings on the board, and two NAND dice in each package. We discuss some key features of the cell structure, design and integration of the Micron 3D 32L (32 layers or 32T, 32 Tiers) FG-NAND device, and compare with Samsung’s 32L and 48L V-NAND device.

    Die size and memory density

    Micron’s 32L 3D NAND die size (168.2 mm2) is much larger than Samsung’s 32L (84.3 mm2) and 48L (99.8 mm2) 3D V-NAND devices. Micron’s 32L 3D NAND memory size is 48 GB/die (384 Gb/die) which is more than 4 times Samsung 32L V-NAND (85.3Gb/die) and 1.5 times their 48L V-NAND (256 Gb/die). In other words, the memory density for the Intel/Micron 32L 3D NAND is 2.28 Gb/mm2, while Samsung’s 32L V-NAND and 48L V-NAND are 1.01 Gb/mm2 and 2.57 Gb/mm2, respectively. FIGURES 1 and 2 show comparisons of memory density and memory array efficiency for the Micron 32L, Samsung 32L and 48L 3D NAND memories. Micron’s 2.28 Gb/mm2 memory density is the same as their announcement in 2015 at IEEE IEDM. They announced another 3D NAND with 768 Gb/die TLC (which is 4.29 Gb/mm2) earlier this year at ISSCC 2016.

    We can find a gap between the two announcements, including memory density difference (2.28 Gb/mm2 and 4.29 Gb/mm2). They might further shrink bitline pitch to 40 nm or expand to 48 layers. Comparing the 32L 3D NAND devices, the memory density on Intel/Micron’s 1st generation 3D NAND is more than two times Samsung’s 32L 3D NAND. Although Micron jumped into the 3D NAND race two years later than Samsung, Micron beat Samsung’s 32L 3D NAND devices and came close to Samsung’s 48L ones by using CMOS circuit under the memory array. We’re looking forward to seeing their 2nd generation (either a modified 32L or a new 48L) FG-NAND.


    FIGURE 1. A comparison of memory density on Intel/Micron 3D 32L NAND, Samsung 3D 32L and 48L NAND.

    FIGURE 2. A comparison of memory array efficiency on Intel/Micron 3D 32L NAND, Samsung 3D 32L and 48L NAND.

    3D memory cell architecture

    As shown on FIGURE 3, the Intel/Micron 1st generation 3D FG-NAND (32L or 32T) has 4 planes with 32 tiles; while Samsung’s 3D V-NAND, either 32L (2nd generation) or 48L (3rd generation), has 2 planes without a tile-like floor plan. An innovative technology from Micron is that CMOS decoders and sense-amps are sitting under the 3D FG-NAND memory array for high memory density (2.28 Gb/mm2). Referring to the memory tiles comprised of page buffer (PB), string drivers and CMOS circuits, the area of unit memory tile is 4.12 mm2. The 1 kB page buffer, string drivers and other CMOS circuits on each memory tile have 2.20 mm2, 0.83 mm2 and 1.09 mm2 areas, respectively (FIGURE 4). As Micron mentioned at ISSCC 2016, placement of the wordline drivers under the array allows for the wordline lengths to be short.


    FIGURE 3. Top metal level and Diffusion level of Micron 3D 32L NAND die.

    FIGURE 4. Memory tile layouts on Micron 3D 32L NAND die.

    Micron’s 32L 3D FG-NAND uses a 4 metal CMOS plus FG-NAND array on common source plate technology. The FG-NAND array has 32 active wordlines, 6 dummy wordlines (3 on the top portion and 3 on the bottom portion), one source-side select gate and one drain-side select gate. All of the wordlines and select gates are on a Si/W-silicide-based common source plate. The NAND array has 40 gates (38 wordlines plus 2 select transistors), which is different from Samsung’s 32L V-NAND which has 39 gates (36 wordlines plus 3 select transistors).

    Micron’s V-NAND uses a vertical Si-channel surrounded by a floating gate (FG) and a control gate (CG), termed a ‘gate all around (GAA)’ structure. The vertical Si-channel and control gate stacked memory cell structure is the same as Samsung’s, however, Micron uses a silicon FG (floating gate) layer instead of Samsung’s SiN charge trap layer (CTL). The FG layer is far better way to store more electrons than a SiN layer. Micron’s 52 nm 32L NAND array vertical cell gate pitch is less than Samsung’s 60 nm 32L V-NAND vertical cell gate pitch. Micron’s memory cell array (or Si-channel hole) height is 2.21 μm, which is 27% lower than that of Samsung 32L (2.9 μm).

    Micron’s 3D FG-NAND cell architecture has a ‘CG/FG first, Channel last’ scheme, while Samsung’s 3D V-NAND cell integration has a ‘Channel first, Gate last’ scheme. Micron’s process involves first making the control gate/dielectric stack. A recess etch would have been used to form cavities for the polysilicon floating gates (FG) and inter-poly dielectrics. The deposition of the tunnel oxide and polysilicon channel would complete then NAND string. An etch-back processes is applied for both CG and FG structures to recess and isolate the gates.

    Micron’s 2D 16 nm node planar thin-FG NAND Flash has a select gate with the same structure as the cell, which has a high-k dielectric stack and a thin polysilicon floating gate. To simplify the manufacturing of the 16 nm cell, the source and drain select gates are constructed in a similar manner as the cell. In contrast, Micron’s 3D FG-NAND device has a select gate composition that is different from cell gate. Here, the source and drain select devices are single gate oxide transistors.

    Placing the select gates and dummy wordlines under and on the memory cell gates looks reasonable from an integration perspective. Intel/Micron and Samsung have the same configuration of dummy wordlines near the select transistors, but Samsung has a SEG (Si epitaxial growth) channel on GST (ground select transistor) structure. Micron uses a single select gate with a thick gate length (thickness) on the drain side, while Samsung has two thin SSTs (string select transistors). FIGURE 5 shows a comparison of 3D cell gate structure on Samsung and Intel/Micron 32L NAND devices.


    FIGURE 5. A comparison of 3D cell gate structure on Samsung and Intel/Micron 32L NAND devices.

    3D NAND competition and roadmap

    When Micron will produce 48L 3D FG-NAND commercial products is an open question. FIGURE 6 shows a NAND roadmap for the major players of 3D NAND products (Samsung, Micron/Intel, Toshiba/SanDisk and SK-hynix). Samsung has 48L V-NAND SSD products and they are developing 64L for their next generation 3D V-NAND. Samsung has been more focused on 3D V-NAND development including yield improvement and 64L V-NAND than next generation 2D NAND (1z nm). Intel/Micron have just entered the V-NAND race with their 32L FG-NAND. Once they successfully release 48L and 64L, if in a timely manner, they may gain market share at the expense of Samsung, Toshiba and SK hynix. Toshiba and SanDisk are scheduled to release their 3D BiCS NAND products to compete in the 3D NAND sector soon.

    Intel/Micron’s 1st generation 3D FG-NAND devices with 32L (or 32T) are quite compatible with Samsung’s 32L 3D V-NAND. Samsung and Toshiba use a CTL (charge trap layer), while Micron adopted thin-FG silicon layer as a storage between channel and CG. Although Micron’s thin-FG layer contains more electrons than Samsung’s CTL SiN layer, the etch-back process used to isolate the FG layers may result in non-uniform FG sizes and coupling ratios. Furthermore, the FG layer is getting smaller and may form nanowire-like or nanodot-like structures on the Si cylinder during the process integration creating performance non-uniformities. Samsung’s CTL scheme does not suffer as much from process non-uniformities giving it an advantage. Additionally the CTL does not require isolation between each of the stacked cell gates.

    Which is better? Intel/Micron’s 32L 3D FG-NAND or Samsung’s 32L (or 48L) 3D V-NAND? From the memory cell structure and process integration viewpoints, Samsung looks better than the Intel/Micron design due to the CTL scheme. From the die efficiency and memory density viewpoints, Intel/Micron’s CMOS circuit layout under the memory array has an advantage over Samsung’s conventional die floor plan. Should Micron scale down the bitline pitch from 80 nm to 40 nm, it would be a memory density advantage to them. We can discuss further after circuit, device and waveform analyses on Intel/Micron’s 3D NAND devices.


    FIGURE 6. NAND technology roadmap.

    JEONGDONG CHOE has more than 20 years of experience of semiconductor process and device integration including NAND Flash, DRAM, logic and advanced memory devices at Samsung and SK-Hynix. He works at TechInsights as a senior technical fellow focusing on memory/logic products, architecture, roadmap and technology.

TechInsights originated in 1989 as Semiconductor Insights. Now, 25+ years later, we are owned by private equity – AXIO Data Group – and are headquartered in Ottawa, Canada with state of the art labs, an expansive research portfolio and over 180 employees worldwide.