This report is a detailed structural analysis (MDSA) of the 21 nm node LPDDR3 DRAM found in the H9TQ18ABJTMC multi-chip memory package. The report contains SEM and TEM cross-sectional images of the metallization, dielectrics, transistors and memory cell; layer-by-layer SEM plan view images of the DRAM array, TEM-EDS and EELS materials analyses, and SRP analysis of the peripheral and array wells.
The LPDDR3 DRAM is fabricated using a 4 metal (Al, Cu, W), tungsten word line, 21 nm DRAM process.
The device features polysilicon peripheral transistors having a multilayer metal/silicide on polysilicon gate structure. The DRAM array features tungsten/TiN buried word lines, 65 nm word line and bitline pitches, a 21 nm half-pitch STI and 0.0043 µm2 cell size.
The reported results are derived from scanning electron microscope (SEM), transmission electron microscope (TEM), energy dispersive X-ray spectroscopy (TEM-EDS), electron energy loss spectroscopy (TEM-EELS) and spreading resistance profiling (SRP).