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Published: 1 May 2014

This report is a detailed structural analysis (LDSA) of the Oracle T5 multicore SPARC processor fabricated using TSMC’s 28 nm HP process. The T5 SPARC processor is a 16 processor core system on chip (SoC) operating at a 3.6 GHz clock. The T5 features two PCI-Express 3.0 controllers on die, four DDR3 on-die memory controllers; along with 16 KB of L1 data cache, 16 KB L1 instruction cache, 128 KB L2 cache for each core; and 8 MB of shared L3 cache. The T5 is fabricated using 13 metal (12 Cu, 1 Al), high-k metal gate (HKMG), gate last 28 nm HP CMOS process from TSMC. The device features <110> channel orientation for the transistors, hafnium oxide/oxide gate dielectric, dual work function metal gates, NiSi NMOS and NiSiGe PMOS source/drain regions and low-k inter-level dielectrics. The device features approximately 30 nm long NMOS and PMOS gates with a 120 nm contacted gate pitch, and 110 nm metal 1 pitch in the SRAM array. The 6T SRAM features a 0.15 µm2 cell size. The reported results are derived from scanning electron microscope (SEM), transmission electron microscope (TEM), energy dispersive X-ray spectroscopy (TEM-EDS), electron energy loss spectroscopy (TEM-EELS) and spreading resistance profiling (SRP).

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