• SoC Design Architecture Blog

  • 10nm SoCs Right Around the Corner

    Contributed by Andy Wei
    Posted: April 10, 2017

    With the recent unveiling of the Samsung Galaxy S8, we are within days of analyzing the first 10nm technology implementations of mobile flagship applications processors. Mobile application processors have been leading the industry adoption of the newest logic technology nodes due to the fierce competition for very large volumes.

    The anticipation for 10nm is especially high because of a long pause in pitch scaling, significant press coverage on the death of Moore’s Law, and a subsequent marketing node naming battle which has seemingly decoupled numerical node names with a physical pitch dimension. The excitement is high as 10nm heralds a start of a new era where technologists begin to implement new scaling solutions which will yet again push out the end of Moore’s Law. With the upcoming 10nm products being released in 2017, 7nm announcements, even 5nm production dates, 3nm research, 7FF+, 8nm, 6nm, 12FDX, 12FFC, 22FDX, 22ULP, 22FFL, as well as the incumbent 16/14nm variants, there has never been this many technology choices to build a leading-edge or near leading-edge SoC. Extensive benchmarking of current SoC implementation and claims of next node implementation is required to make the best decisions for the next generation of SoC or IP designs.

     

    Fortunately, at TechInsights, we have techniques which can quantify actual SoC scaling from functional block and die utilization, down to standard cell utilization and routing efficiency. Actual routed gate densities can be determined, and along with costing and transistor performance characterization, TechInsights can provide all the data required to benchmark SoCs. Which manufacturer at which foundry is actually leading in area, performance, and cost? How will these trends continue into the next technologies?

    As shown below, our benchmarking toolbox includes floorplan and functional block analyses, standard cell utilization and routing efficiency, process analysis for yield risks and costing, as well as characterization of actual transistor performance. Our extensive data sets and analyses are made available through our ChipSelect SoC Design Architecture and ACMOS Advanced Logic Process programs.

    Over the release of 10nm products in 2017, we’ll be connecting the dots where 10nm implementations are relative to 16/14nm, 20nm, and 28nm SoC implementations, and what this means for the next nodes on or near the leading edge. Please check back here for updates in a couple of weeks!

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