NAND flash has become an increasingly important part of today’s technological society with USB flash drives, smartphones, digital cameras, tablet PCs and iPads becoming a more and more integrated part of society on which we rely on. As a result, revenues are rising rapidly. This will mark the second straight year during which the NAND flash market is expected to display, double digit growth at 13% moving revenue to $28 Billion in 2014. The three largest markets for NAND Flash are smartphones, solid state drives (SSDs) and tablets in that order. Smartphones alone consume over a quarter of the world’s flash, an amazing ramp-up considering the first iPhone was released in 2007. SSDs are seeing significant consumer demand, but also in the large data server market as people migrate their information storage to the cloud and the cost of ownership of enterprise SSDs is dropping below their HDD equivalents. The NAND Flash Roadmap Summary shows the expected rollout times for NAND flash process nodes of the largest manufacturers compared to the ITRS timeline. Complimentary Technology Roadmap on NAND Flash Expect to see 3D NAND flash in the market from late 2014 and beyond The International Technology Roadmap for Semiconductors (ITRS) is a best opinion amongst representative experts on timelines for specific technologies; NAND Flash in this case. The ITRS roadmap predicts when the entire industry is expected to manufacture at a specific node, not the date for first release. The increase in demand is expected to continue, and the four main manufacturers (Samsung, Toshiba/Sandisk, SK Hynix and Intel/Micron) are working hard to maintain margins by increasing the storage density. There are two main ways to do this; decrease the process linewidth, and store multiple bits on a single floating gate (a technique called Multi-Level Cell or MLC storage). Both of these approaches hit severe problems as the process node is reduced. At smaller linewidths, the leakage current between the floating gate and the control gate increases resulting in reduced reliability. MLC becomes very challenging at low voltage supplies and small linewidths as the charge stored on the gate becomes exceedingly small; tens of electrons resolve different bits on the cell. The control circuits and process stability required to achieve this are highly innovative. To get to the next density level, manufacturers are planning to shift from “2D” designs to “3D”. Conventional 2D designs create the memory cells in a two dimensional array on a silicon substrate. 3D design move into the third dimension by stacking cells on top of each other enabling significant density increases. The NAND strings used in this approach are arranged to conduct charge either horizontally (parallel to the substrate) or vertically. Each approach offers advantages and it is not yet clear which approach will be adopted.